The present invention relates to a data processing system employing a shared direct memory access controller for connecting a plurality of subsystem device controllers to a memory under the control of a microcomputer which serves as the central processing unit of the system. Microprocessors are a fairly recent development and are receiving wide attention in the data processing art. See for example Fortune Magazine, November, 1975. While microcomputers are of extremely small size, can be extremely fast in operation, and are relatively inexpensive compared to prior art computers, they sometimes have undesirable limitations. For example, the Intel 8080 microcomputer has only two instructions for communicating with external devices. One of these is for controlling input operations and the other is for controlling output operations. This characteristic places severe limitations on the use of this particular microcomputer in a system employing a number of peripheral devices of diverse characteristics, particularly where it is desired to provide direct memory access whereby the peripheral devices may communicate with the memory at the same time the microcomputer is engaged in other operations.
The concept of direct memory access is well known in the art. Generally speaking, this concept allows a central processing unit to load a subsystem device controller with the instructions and data necessary to initiate and carry out a data transfer between the memory and the peripheral device connected to and controlled by the subsystem device controller. Once the subsystem controller has been set up, the central processing unit is then free to carry out other operations in the system while the subsystem device controller itself controls the transfers between memory and the peripheral device.
In the prior art, it has been customary to provide each subsystem device controller with all of the circuits necessary for carrying out the data transfers between its peripheral device and the memory. Furthermore, each of the subsystem device controllers has been directly connected to a system bus to which the memory and cenral processing unit are also connected. There are some functions which must be performed by each of the subsystem device controllers regardless of the type of the peripheral device they serve hence the presently utilized arrangement requires an unnecessary duplication of circuitry in each of the subsystem device controllers in order to carry out these functions.